Lesson 9 — What Comes Next?
How Do Chips Actually Work?
Learning Material
1 pagesLesson 9 — What Comes Next?
Understanding the Complex: How Do Chips Actually Work?
In February 2024, TSMC announced that it was beginning risk production of its 2nm process node, with volume production expected in 2025. "2nm" — like "5nm" and "3nm" before it — is partly a marketing designation rather than a strict physical measurement; the actual transistor dimensions are somewhat larger. But the underlying capability is real: denser packing, lower power consumption per operation, and higher performance per unit area than any chip in mass production.
The announcement was significant not because 2nm is the end of the road, but because it confirmed that the industry is still moving — still pushing the frontier, still finding engineering solutions to problems that were supposed to be insurmountable.
What comes after 2nm? And what happens when silicon itself runs out of room?
Near-term: Gate-All-Around and the next few nodes
The transition from FinFET to Gate-All-Around (GAA) transistors — already underway at Samsung for its 3nm process — represents the next major architectural step. In a GAA transistor, the gate wraps entirely around a channel made of nanosheets or nanowires, giving it maximum electrostatic control and allowing continued scaling.
TSMC is expected to introduce GAA transistors at its 2nm process, with further iterations at 1.4nm and beyond. The industry's leading research institution, IMEC, publishes roadmaps that project continued scaling to below 1nm — though at each step, the engineering challenges grow and the economics of further miniaturization must be justified by performance gains.
Beyond transistor architecture, improvements are coming from new materials. Conventional silicon is being complemented by other semiconductors — gallium nitride (GaN) for power electronics, indium gallium arsenide (InGaAs) for high-frequency applications — that have properties silicon can't match in specific domains.
Medium-term: 3D integration and chiplets
Perhaps the most important near-to-medium-term trend isn't in making individual transistors smaller, but in stacking chips vertically. Three-dimensional integration — placing multiple chips on top of each other, connected by dense arrays of microscopic copper pillars (through-silicon vias, or TSVs) — allows architects to create extremely short electrical paths between different functional units.
AMD's EPYC processors use a "chiplet" approach: rather than one large, expensive-to-manufacture die containing all the CPU cores, cache memory, and I/O interfaces, the chip is assembled from several smaller dies. Smaller dies have higher manufacturing yields (fewer defects per die), can be sourced from different fabs optimized for different process nodes, and can be mixed and matched for different product tiers.
The "hybrid bonding" technique — connecting dies with direct copper-to-copper bonds rather than solder bumps — allows connection densities that approach the density of connections within a single die, enabling seamless integration of separate silicon components. AMD, Intel, TSMC, and others are all investing heavily in this direction.
Intel's recent "Foveros" packaging technology and TSMC's "CoWoS" (Chip on Wafer on Substrate) represent current implementations. Nvidia's H100 and H200 AI accelerators use CoWoS to integrate HBM (high-bandwidth memory) alongside the GPU die in a single package.
Long-term: what replaces silicon?
Several candidate technologies are under investigation, each with distinct advantages and challenges.
Carbon nanotubes are cylinders of carbon atoms that can conduct electricity with extremely low resistance and can be made into transistors far smaller than silicon-based ones. IBM has demonstrated carbon nanotube chips in research settings. The challenge is manufacturing: growing uniform, correctly oriented carbon nanotube arrays at wafer scale remains extremely difficult.
Neuromorphic computing takes a different approach: rather than the conventional von Neumann architecture — where a processor fetches and executes instructions from memory sequentially — neuromorphic chips mimic the structure of the brain, with computation and memory integrated and information processed in massively parallel, asynchronous fashion. Intel's Loihi chip and IBM's TrueNorth are examples. For specific workloads — pattern recognition, low-power sensing — neuromorphic chips can be far more efficient than conventional processors. They are not, however, general-purpose replacements.
Quantum computing — using quantum mechanical effects like superposition and entanglement to perform computations impossible on classical computers — is perhaps the most anticipated long-term technology. Current quantum computers exist and can solve specific problems that classical computers cannot, but they require extreme cooling (to near absolute zero), are error-prone, and have a small number of usable qubits. Whether useful fault-tolerant quantum computers will be available within a decade, or will require several decades more, is a matter of genuine uncertainty.
The geopolitical trajectory
The technological roadmap plays out against a geopolitical backdrop that is unlikely to stabilize quickly. US export controls on advanced chips and chip-making equipment to China are likely to persist and potentially intensify. China will continue its domestic semiconductor development efforts, achieving incremental progress that may eventually close some of the gap with the frontier.
The CHIPS Act investments are creating new fab capacity in the US — TSMC's Arizona fab is expected to enter production at N3P (roughly equivalent to TSMC's 3nm process) by 2026. Intel's Ohio fabs are under construction. Europe's first leading-edge fab — a TSMC plant in Dresden, Germany, jointly funded by the EU, Germany, and TSMC — broke ground in 2024.
None of this will eliminate the concentration of leading-edge production in Taiwan within the next decade. But it represents the beginning of a more geographically distributed supply chain — one that may be more resilient, if also more expensive, than the current structure.
Next lesson: What If...? — three thought experiments about disruptions, alternatives, and futures that illuminate what's at stake.
Reading time: approx. 9–10 minutes